The present invention relates to maintaining linearity of the hardware circuitry for a wide frequency range, and more particularly, to a method for performing phase shift control for timing recovery in an electronic device, and an associated apparatus.
In ultra-high speed Serializer/Deserializer (SerDes) or Analog-to-Digital Convertor (ADC) applications, the sub-rate (e.g. half-rate, quarter-rate, oct-rate, etc.) Serdes or interleave ADC architecture may have become the main stream since it is possible to reduce the samplers timing budget or the noise specification requirement. While the techniques progresses, however, some problems such as some side effects may occur. For example, the related art may suffer from one or more of high power consumption, large area, and poor timing recovery. Thus, a novel method and associated architecture are required for achieving lower power consumption, smaller area, and better timing recovery.